The present invention relates in general to integrated circuitry, and in particular to an improved current-controlled open-drain output driver.
Since the adoption of the reduced instruction set computer (RISC) architecture, the central processing unit (CPU) speed has been increasing rapidly year after year. On the other hand, the speed of memory devices such as dynamic random access memory (DRAM) has not nearly kept up with the rapid increase in CPU speed. In fact, the gap between the respective speeds of CPUs and memory devices has been widening in recent years.
Since memory is a common component in digital devices, the speed of the memory in many applications affects the overall performance of digital devices. As a practical matter, a CPU in most cases cannot effectively perform its functions until and unless it receives the requisite data from the appropriate memory device. Hence, the speed difference between CPUs and memory devices has created a performance bottleneck.
In an effort to catch up with the rapid enhancement of CPU performance, a number of improved memory devices, such as Rambus DRAM (RDRAM) and Synchronous DRAM (SDRAM), have been introduced. These improved memory devices generally provide high bandwidth memory transfers by using high speed output drivers. Further information regarding high bandwidth DRAMs can be found in A. Hatakeyama et al., "256 Mb SDRAM Using a Register-Controlled Digital DLL," ISSCC Digest of Technical Papers, pp. 72-73, February 1997; C. Kim et al., "A 640 MB/s Bi-Directional Data Strobed, Double-Data-Rate SDRAM with a 40 mW DLL Circuit for a 256 MB Memory System," ISSCC Digest of Technical Papers, pp. 158-159, February 1998; and N. Kushiyama et al., "A 500-Megabytes/s Data-Rate 4.5M DRAM," IEEE J. Solid-State Circuits, vol. SC-28, pp. 490-498, April 1993.
FIG. 1 illustrates an example of a high speed output driver circuit in accordance with an RDRAM design. An NMOS transistor (NM) has an open-drain design. The drain node of the transistor (NM) is connected in series with an off-chip termination resistor 10 and a termination voltage source 12 through an off-chip transmission line. Typically, the termination resistor 10 has a value of R.sub.T =40 .OMEGA. and the termination voltage source 12 may have a value of V.sub.TT =1.8V. The drain node voltage of the transistor (NM) is used to provide the output voltage used to drive external devices coupled to the pad (PAD). Hence, the drain node voltage, or conversely, the voltage swing across the termination resistor 10, should ideally be kept at a stable level. The voltage swing across the termination resistor 10 is determined by the drain (or output load) current I.sub.OL of the turned-on open-drain NMOS transistor (NM). The drain current in turn is affected by the supply voltage, which in this case is the termination voltage source 12, and variations in temperature.
Circuit techniques have been developed to keep the output current I.sub.OL stable and insensitive to variations in temperature and supply voltage. An example can be found in N. Kushiyama et al., "A 500-Megabytes/s Data-Rate 4.5M DRAM," IEEE J. Solid-State Circuits, vol. SC-28, pp. 490-498, April 1993, and Thaddeus J. Gabara et al., "Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers," IEEE J. Solid-State Circuits, vol. SC-32, pp. 407-418, March 1997. In Kushiyama et al., the open drain NMOS transistor is split into binary-weighted transistors, the ON/OFF condition of which is determined by a digital code. This digital code is generated by an external source in the system and sent to the output driver periodically. The generation of the digital code by an external source necessarily causes overhead in the system. Accordingly, a technique would be desirable for reducing the overhead of generating a digital code from an external source for compensation of temperature and supply voltage variations.